1. Field of the Invention
This invention relates to a novel structure to aid in the testing of high-density electronic systems such as Integrated Circuit (IC) chips.
2. Description of the Prior Art
The advanced semiconductor technology with its ability to integrate a large number of electronic circuits on a single Integrated Circuit (IC) has brought down the cost of functions, such as computers, by many orders of magnitude. The resulting reduction in size, weight and number of interconnections have also improved the reliability and portability of the electronic systems. However, the higher number of circuits within an IC has created one big problem-how to test the IC to verify that it will perform according to the specifications under all circumstances and if it does not perform according to the specifications then how to determine what is exactly the nature of the fault?
The testing of a complex IC requires that a large number of test-points be available on the IC to control and to observe the states of all the circuits within it. The test-points are defined as the electrical nodes on the Integrated Circuit which are accessible to test-electronics external to said Integrated Circuit for the purpose of either measuring the signals present at said electrical nodes or injecting a signal at said electrical node. The cost of adding more test-points within an IC is that the test-points, which are generally contacted by mechanical means, occupy a lot of area-causing the IC to be significantly larger and hence more expensive and slow. The locations on the IC where external test electronics can be electrically connected to the IC are referred to as probe-points. Various test structures have evolved over the past few years to increase the number of test-points on an IC while minimizing the area occupied by the probe-points. These techniques are described below.
The most common test structure is based on the use of signal input and output pads on an IC. These input and output (also called I/O) pads are provided on every IC so that it can communicate with the eternal world and they are called the primary input and output pads. In the commonly used test techniques, different test patterns are presented to the primary input pads of the IC and the signals on the primary output pads of the IC are observed to verify that the IC chip functions correctly under all test situations.
In many instances the primary inputs and outputs do not provide adequate controllability or observability over the circuits within the IC to test it completely. Sometimes, additional test-points are added to the IC and brought out to additional probe-points where they may be connected to external test electronics by the means of mechanical probes. An article entitled "Test Point Placement to Simplify Fault Detection" by J. P. Hayes et al. in IEEE 1973 Symposium on Fault Tolerant Computing (FTC-3), p. 37, shows a method for additional test-points placement to improve testability of an Integrated Circuit. This reference, however, does not show a structure for a multi-dimensional, easily accessible array of test-points as disclosed in the present invention. The above schemes becomes impractical when the number of circuits within the IC becomes greater than a few thousands. In such cases the so-called "SCAN-TEST" (Ref. T. W. Williams and K. P. Parker, "Design for Testability--A Survey" Proc. IEEE, VOL. 71, pp. 98-112, Jan. 1983) or the so-called "Level Sensitive Scan Design" (Ref. E. B. Eichelberger and T. W. Williams, "A Logic Design Structure For LSI Testing", Proc. 14th Design Automation Conf., June 1977, 77CH1216-1C, pp. 462-468; also, E. J. McClusky, "Built-in Self-Test Techniques" and "Built-in Self-Test Structures" IEEE Design and Test, Vol. 2, No. 2, pp. 437-452, April 1985.) techniques are used. These techniques are based on the storage elements such as flipflop circuits within the IC, which are externally controlled to either generate a desired signal at a given test-point within the IC chip, or to observe a signal at a given test-point within the aforementioned IC. Additionally, these storage elements are serially connected together as shift-registers so that all said storage elements can be serially accessed by external electronics while requiring very few additional probe-points. Thus, these techniques succeed in introducing additional testpoints on the IC, in addition to those provided by the primary inputs and outputs pads on the IC chip. The major disadvantage of these techniques is that an areaconsuming and speed-degrading flip-flop circuit is needed for each additional test-point that is added to the IC.
U.S. Pat. Nos. 3,806,891; 3,761,675; 4,293,919 and 4,513,418 assigned to the IBM Corporation teach that the flip-flop circuits on the Integrated Circuit can be used as additional test-points and that they can be serially connected together as a shift-register to allow access to them through very few probe-points. These references can be distinguished from the present invention in that they provide a limited number of additional test-points, equal to the number of flip-flop storage elements used for test purposes and in that these additional test-points are connected together in only one dimension, forming a serial shift-register. The present invention does not demand space consuming flip-flop storage elements and the test-points are accessed in a two or more dimensional fashion to provide a significantly higher number of test-points on an IC than available in the techniques described in the above referenced patents.
U.S. Pat. No. 4,340,857 filed July 20, 1982 in the name of P. P. Fasang teaches the use of Linear Feedback Shift Registers (LFSR) for the purposes of test pattern generation as well as for test output data compaction and analysis. This reference does not show a multidimensional, grid-based test structure for providing increased number of test-points on the Integrated Circuit. U.S. Pat. No. 4,423,509 filed Dec. 27, 1983 in the name of N. H. Feissel shows yet another technique to use flip-flops as additional test-points on an Integrated Circuit. This reference can be distinguished over the present invention in that it produces only one additional test-point for each flip-flop employed and that it does not teach a multi-dimensional grid structure to generate a large number of test-points.
As the integration levels of the ICs increase to the 10,000 gates and above levels the test techniques referenced above become quite inadequate because they can not economically excite every possible signal combination and can not inquire the state of every circuit within the IC. Thus, serious danger exists that all the faults in an IC will not be found before the IC is employed in a product. The IC may later fail in a critical application, forcing large redesign costs, product withdrawals and creating the potential for very large liabilities.
Recently, several new test techniques have been proposed which seek to reduce the size of the probes-points to allow more test-points within an IC. These new techniques employ either electron beams or laser light beams to probe the test signal within the IC. The physical diameters of the laser or the electron beams can be made extremely small as compared to the mechanical probes used previously. Thus these techniques do not require large, area consuming probe-points. The availability of such beams removes the restrictions placed by the limited number of primary I/O pads on the IC. Most signal nodes can now be probed by these beam techniques. The cost of such techniques is however quite formidable since they require very sophisticated alignment and focussing systems, vacuum chambers and expensive laser or electron beam sources. Other disadvantages of these beam techniques are that it allows the control or the observation of only a few nodes on the IC at any one time and that it takes a very long time to test ICs.
The "Cross-check" test structure of the present invention solves the above problems by providing a large number of test-points for a detailed testing of an IC chip and yet does that while occupying very little area on the IC and does not require expensive equipments such as vacuum chambers and electron or laser beams. This is accomplished by employing a two or more dimensional array of test-points on the IC. Another distinguishing feature of the present invention over the prior techniques cited above is its ability to immediately pin-point the exact location of a fault without the need for lengthy calculation. This allows rapid debugging and verification of a new design.